Parity-based Soft Error Detection with Software-based Retry vs. Triplication-based Soft Error Correction - An Analytical Comparison on a Flash-based FPGA Architecture

Field-programmable gate arrays (FPGAs) are often utilized in space avionics. To protect the FPGA logic against the ionizing radiation effects in space, redundancy in form of concurrent error detection can be used. In this work, we present a comparative study of a parity-based error detection with software-based retry, and a triple modular redundancy technique on a known flash-based FPGA architecture (Microsemi ProASIC3). We compare critical path delay, circuit area overhead, multiple bit error probability and error correction time penalty. Our analysis shows that a solution based on parity-based error-detection can at least save about half of the resource overhead caused by triplication of the flip-flops if the target circuit can be functionally isolated from the rest of the circuit in the FPGA and if the software supports retransmission of access requests.